FPGA implementation results of an open core IEEE 754-based FPU with non-linear arithmetic support are shown. Non-linear operations are implemented using variations of the CORDIC algorithm, and are tested on a commercial FPGA. The unit provides results both on 32-bit and 64-bit FPU formats, with error bounded to 0.81501% for the cosine operation, 0.91367% for the sine operation, and 0.129% for the natural logarithm operation, using sixteen iterations in all cases, and a 64-bit floating point representation. Dynamic power is under 11mW for each non-linear operational block, at a 100MHz clock speed.