This paper describes the CMOS implementation of the variable output voltage, multi-phase switched capacitor step-up DC-DC converter with SAR-based regulation scheme. The number of target voltages generated using n-flying capacitors is of the order of 2n. A scheme for selection of switch is presented. Expressions for equivalent series resistance (Req), conduction, switching power loss and efficiency are obtained and compared with the spice simulation results. The converter has an inherent capacitive DAC that can be used for digital gain control along with a comparator to get the desired output voltage. The step-up open loop converter circuit for the gain of 4/3 is described and analysed by varying the switching frequency. An open loop converter efficiency of about 78% is achieved with 4% bottom plate parasitic capacitance for a load current of 1 mA and input voltage of 0.6 V at 4 MHz of switching frequency. The digital control circuit using inherent capacitive DAC is designed and simulated in Cadence Analog-Mixed signal flow. The layout design using MIM cap has been done and back annotation results are presented.