In recent years, the wide-voltage-operating-range circuit has drawn great attention because of its ad-hoc performance and energy efficiency to meet the demands of various applications. The circuit can either obtain the best possible energy efficiency at low voltage or achieve high performance at nominal voltage. A big challenge is the severe Process, Voltage, and Temperature variations under the nanometer process. Thus, when working at the near-threshold region, it may result in timing failure and fails to achieve the possible high-energy efficiency. In this paper, an Adaptive Voltage Scaling (AVS) method based on in-suit timing monitor is proposed with a tunable detection window. It resolves the above problem by monitoring the paths’ timing and adjusts the supply voltage adaptively. It is applied on a system-on-chip circuit consistig of a CPU, ESRAM, an AES cryptographic circuit, and peripherals. Fabricated using the SMIC 40nm CMOS process, it can work at 0.6 to 1.1 V with remarkable power savings. Simulation results show that in the super-threshold voltage region, the supply voltage can be reduced from 1.1 to 0.86 V, enabling a maximum of 50% power saving at the FF corner, −25°C as compared to conventional non-AVS design. In the near-threshold region, the supply voltage is reduced to 0.48 V, with a power saving up to 70% at the FF corner, 125°C as compared to a non-AVS design.