Process-induced mechanical stress has been known as a technique to boost carrier transport of transistors. Basically, stress affects leakage consumption, threshold voltage, and mobility by making changes in band structure of silicon. Stress-enhancement techniques are highly dependent on layout structure. In past years the device parameters have been modeled versus some of the layout parameters incorporating in stress mechanisms. Besides, mechanical stress is known as one of the sources of layout proximity variation categorized under systematic variations. As a result, stress could play a key role in performance variation of Integrated Circuits. In this paper, we model the timing of stress-induced logic gates. Our modeling approach relies on the fact that stress affects mobility and threshold voltage of transistors. The timing of stressed gate is expressed by the product of unstressed gate delay and a parametric coefficient standing for variations of mobility and threshold voltage. Furthermore, the accuracy of our modeling is another key feature of our work. The proposed modeling methodology is verified for basic digital logic gates in 45 nm, 65 nm, and 90 nm Predictive Technology Models (PTM). Simulation results performed by HSPICE and the results achieved by our modeling exhibit less than 3% Mean Percentage Error (MPE).