A 28 nm CMOS-bulk lowpass analogue filter architecture is hereby proposed. The filter is based on an improved Active-Gm-RC structure, where both poles of a Miller-compensated operational amplifier (OPAMP) have been used for synthesising a third-order filter. Several well-known issues related to the 28 nm process node have been hereby mitigated by proper circuit/design techniques, enabling large signal-to-noise ratio (SNR) and 13.5 dBm IIP3. The proposed circuital solution performs 59 dB-SNR at 340 µW power consumption from a single 0.9 V supply-voltage. This allows one of the higher figure-of-merit (156 dB) in sub-1 V analogue filters state of the art.