In this paper FPGA implementation of a simple median based technique for selective image encryption is presented. Image encryption imposes heavy resource requirements on the hardware platform due to large size of data. Although Advanced Encryption Standard (AES) provides a high level of security to the image, it takes more time when used for image encryption. The technique presented in this paper first divides the image into blocks and then using median value of the pixels of the block decides the pixels that are to be encrypted. As the image is partially encrypted, a mask is formed along with the image that keeps the record of encrypted and unencrypted pixels. The results show significant reduction in the amount of data encrypted as well as time required for encryption while hiding the more important visual content. FPGA implementation and analysis of results show little overhead on area requirements. Decryption of partially encrypted images is suitably performed by designing a counter algorithm for processing mask and decrypting the image selectively. Peak signal to noise ratio and mean square error are calculated for sample images to show security obtained via selective encryption.