As the complexity of evolving integration circuits and number of cores in each chip increases, the performance aspect becomes an important issue while designing complex chips. Networking becomes difficult in such systems when compared to conventional systems. A special networking technique called Network on Chip is used in SoC to address the above problem. In this paper, two techniques such as Platform level design and Modified Random Arbiter combined with deterministic XY routing algorithm are proposed to improve the performance of NoC. For improving the NoC performance, the Platform level design technique is used for forwarding the error free packets to the cluster level network. After the error free packets are received by the router, its random arbiter will service all the incoming packets without stacking in a faster manner. This combined technique optimizes the packet storage area and also improves the performance of NoC by avoiding packet collision, deadlock and live lock conditions.