High-k metal gate (HKMG) has been implemented in production for nearly 10 years. As scaling of HKMG on bulk Si is reaching its limit, alternative device architecture such as FINFETs and FDSOI are being pursued. FDSOI is well suited for applications needing a balanced trade-off among power, performance and cost, such as the Internet of Things (IoTs). Here we show that compared to HKMG on bulk Si, HKMG FDSOI transistors have less VT variation due to its undoped channel. Furthermore, FDSOI unique back-biasing capability offers additional knob to further reduce VT variation. There are, however, a few challenges that must be overcome for successful integration of FDSOI in CMOS. Those challenges such as preventing thin SOI channel erosion, maintaining strain in channel SiGe, preventing oxygen ingress in gatestack, obtaining a low overlap capacitance and growing raised source/drain epi will be discussed.