This paper describes the implementation of a new architecture to multiply signals with time-mode representations. The exponential relationship between voltage and time in an RC circuit is utilized to implement time-mode logarithmic and exponential functions needed to realize a time-mode analog of the translinear principle. Addition of time-mode variables is achieved through the natural progression of time equal to the sum of the input times. By combining these two techniques, an analog multiplier can be implemented almost exclusively with passive circuits and digital primitives. Therefore, the circuit performance could benefit from CMOS scaling trends. A circuit level implementation in a 180nm CMOS process achieves 0.26% linearity error and consumes 9.5pJ per operation. Both behavioral and post layout simulation results are presented.