A 60-GHz wireless transceiver with dual-mode power amplifier (PA) for IEEE 802.11ad in 65nm CMOS is presented. Stacked-transistor technique is employed in the output stage of the PA to boost the output power. A 2-bit switched-capacitor array is employed in the mixers for four-channel coverage. Measurements show that 12.6/8.9 dBm TX output power at 58.92 GHz has been achieved in the high power (HP)/low power (LP) mode, respectively, while the cascaded RX gain is 62–65 dB in CH.1–3 with 28-dB dynamic range. The chip occupies 1.7×2.0 mm2 chip area and consumes 349 mW/205 mW in the TX HP/LP mode and 94 mW in RX mode.