With the development of integrated circuit technology, the NoC(Network-on-Chip) has become a research hotspot in recent years. In this paper, we analyze the relevant theories of NoC, especially about the NoC router, as it plays a very important role for connecting the network. We design a low latency NoC router based on the wormhole virtual channel switching, and implement it on RTL (Register Transfer Level). In addition, a two clock-cycles pipelined design pattern is used to improve the efficiency of the router. Finally, we use the “testbench” to test the router's functions with different input signals. The development tool is ISE provided by the company of Xilinx, and combined with Modelsim for waveform simulation.