This paper is devoted to the architecture development, layout design, device-technological and circuit-topological computer simulation of elements based on single-level and multilevel silicon-on-insulator (SOI) structures, which can be the basis for creating components of analytical and sensory microsystem-on-chip. The architecture and layouts of analytical microsystem-on-chip were developed. Optimized gate array basic cell was developed and library elements on that base are designed. Three-dimensional architectures “silicon-on-insulator” under the surface of the silicon wafer are proposed and simulated. Electrical and time characteristics of individual elemens of microsysem-on chip are defined by schematic simulation.