Although the speed of a digital-to-analog converter (DAC) can reach 100GS/s in recent studies, the achievable effective number of bit (ENOB) is still significantly low. The low ENOB limits the high speed DAC application in high-data-rate transmitters. This paper analyses the required DAC resolution for different modulation orders, which is determined by error vector magnitude (EVM). To verify the output, a high-data-rate quadrature-amplitude-modulation (QAM) transmitter is modeled. Each block is modeled in Verilog/Verilog AMS. According to the model, a data-rate of 20 Gb/s transmitter with 16-QAM and 7 bit DAC is simulated. Even if taken phase error of 5 degree and gain mismatch of 1.3 dB into account, the model works properly. Adjacent channel leakage ratio (ACLR), at 1-dB compression point of 35 dBm, reduced from −29.5 dBc to −23.3 dBc.