A fully integrated successive-approximation (SAR) switched-capacitor (SC) DC–DC converter is presented that overcomes the coarse output voltage resolution limitation of traditional SC converters. An SAR SC converter cascades multiple stages of 2:1 SC converters, and achieves a fine-grained conversion ratio resolution of ${V_{{\rm IN}}}/{2^N}$, where ${V_{{\rm IN}}}$ is the input voltage and $N$ is the number of stages. As the SAR SC converter generates the output voltage through SAR, each stage of 2:1 SC converter provides a fixed voltage level, requiring minimal configuration change for regulation. Analysis shows that the SAR SC converter has a slow-switching-limit output impedance increasing proportionally to ${\text{log}}_{2}$ (number of resolution), and switching loss of bottom-plate parasitic capacitor decreasing with the number of stages. As a test chip, an SAR SC converter with 7 b resolution is fabricated in 180 nm CMOS process and implemented by cascading 4:1 and five 2:1 two-phase interleaving SC stages. It achieves 31.25 mV voltage resolution with output voltages over 0.4 V at ${V_{{\rm IN}}} = 4\,{\text{V}}$. Using this fine grain voltage regulation approach, line and load regulations are implemented with a feedback/feedforward controller with peak efficiency of 72% for load currents from $0\,{\text{to}}\;300\,{\upmu \text{A}}$. The test chip occupies $1.69\,{\text{m}}{{\text m}^{2}}$ and utilizes on-chip capacitors of 2.24 nF in total.