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Schottky source/drain Ge-based n-and p-MOSFETs with sub-1-nm EOT and significantly reduced parasitic resistance were demonstrated for the first time. This technology involves two key processes: thermally stable high-quality metal/high-k/Ge gate stack and self-aligned formation of Fermi level pinned and unpinned NiGe/Ge junctions. The P+ implantation into embedded NiGe S/D and subsequent low-temperature annealing were effective in reducing effective electron Schottky barrier height (eSBH) at NiGe/Ge interfaces.