The overlap between gate and source/drain electrodes gives rise to parasitic capacitance ( $C_{\text {gd}}$ /), which causes RC signal delay in thin-film transistor (TFT) circuits. Here, we show that in amorphous-indium–gallium–zinc-oxide TFTs, offsets as large as $0.5~\mu \text{m}$ , result in only slight reductions in drain-current, such that (compared with single-gate TFTs with 2.5- $\mu \text{m}$ gate-to-source/drain overlaps) an overall three times increase in switching speed can be achieved in dual-gate TFTs with offset top-gates shorted to offset bottom-gates. The high switching speed ( $\sim 18$ ns/stage delay), which is a combined effect of the bulk-accumulation achieved by shorting the two gates and zero $C_{\text {gd}}$ , results in high-speed amorphous oxide TFT-based circuits.