Silicon-Germanium (SiGe), used to boost pFET performance and enhance the properties of high- ${k}$ metal gate devices, is grown by selective epitaxy on silicon. Since device parameters depend critically on the deposited SiGe thickness, we apply several advanced techniques to control deposition. Feedback and feed-forward of growth rate data is used to control deposition tools. We also apply a pattern-density based predictive growth rate, since pattern density effects cause the deposited thickness to be different across different product chips under otherwise identical conditions. We use run to run analysis of deposition data and a feature of the deposition tool to tune cross wafer deposition rates for optimized uniformity. Finally, we consider local (within chip) growth rate variation. We demonstrate that the deposited layer thickness is in acceptable range for device performance across a product chip.