With the introduction of new material (e.g., ultra-low-K inter-metal dielectrics) and package technology (e.g., laser grooving), there are new challenges on product reliability, especially on environmental stress tests related to film adhesion. To better understand the impacts of these changes on field applications, a new evaluation method, the die pull (DP) test, was proposed to assess the inter-layer adhesion. The proposed DP test provides quantitative indices on wafer back-end process robustness verifications during chip-package-interaction (CPI) verifications. However, two major issues need to be fixed on the sample preparations: the low successful rate and the long cycle time. After a carefully designed DOE, we successfully achieved a high successful rate, as well as a shortened sample preparation cycle time (from > 2-day to < 8-hr). This greatly facilitates CPI process improvements and leads to significant process enhancements in a much shorter period of time.