The impact of program/erase (P/E) cycling on the read current fluctuation of 65nm NOR Flash memories is studied in detail. Random telegraph noise (RTN) and 1/f noise analysis are employed to characterize the process induced trap (PIT) and the stress induced trap (SIT) in the tunnel oxide of the floating gate memory cells. The relationship between RTN traps and the read current fluctuation after different P/E cycles is analyzed from a microscopic perspective. Experimental results show that discernible transition between RTN and 1/f noise can be detected at the initial phase of the cycling (<100 cycles), depending on the gate bias voltage (Vg). As the cycle number increases, the transition phenomenon disappears and 1/f noise dominates. This phenomenon can be detected both in program and erase states, and is interpreted by spectroscopy analysis of PIT and SIT.