Few years ago, cryptography based on elliptic curves was increasingly used in the field of security. It has also gained a lot of importance in the academic community and industry. This is particularly due to the high level of security that it offers with relatively small size of the keys, in addition to its ability to the construction of original protocols which are characterized by high efficiency. Moreover, it is a technique of great interest for hardware and software implementation. Pairing-friendly curves are important for speeding up the arithmetic calculation of pairing on elliptic curves such as the Barreto-Naehrig (BN) curves that arguably constitute one of the most versatile families. In this paper, the proposed architecture is designed for field programmable gate array (FPGA) platforms. We present implementation results of the Miller's algorithm of the optimal ate pairing targeting the 128-bit security level using such a curve BN defined over a 256-bit prime field. And we present also a fast formulas for BN elliptic-curve addition and doubling. Our architecture is able to compute the Miller's algorithm in just 638337 of clock cycles.