In power converter design, especially in high power applications, considerable effort have been made on developing DC link capacitor with low stray inductance for the purpose of loss reduction. However, considering practical design requirement, lower stray inductance is not necessarily beneficial for the system. Study on current balancing across capacitor units is performed in this paper. Analysis shows that higher busbar stray inductance can help to improve capacitor internal current balancing during switching transient. An optimization between current balancing in capacitor units and voltage overshoot on semiconductor device should be taken into consideration for converter design. A single pulse test (SPT) setup in half-bridge configuration using 4.5 kV Si-IGBT StakPak power modules is built to verify the theoretical analysis.