As the ESD stress is becoming more and more important for integrated circuits (ICs), the ability to predict IC failures becomes critical. In this paper, an 18 MHz D flip-flop IC is characterized and its behavioral model is presented. The resulting IC model is validated in the setup according to the ISO 10605 standard. A complete model of the setup combining the IC behavioral model and the passive parts of the setup is built to estimate the failure prediction accuracy in a totally simulated environment. The results show that the model can predict the triggering level with the error of less than 20%.