An energy recovering scheme for 40% savings in clocking power with 40% driver active area reduction is demonstrated. A new resonant driver that generates tracking pulses at each transition of clock for dual edge operation across scaled frequencies is proposed. Pulsed resonant (PR) clocking is designed to drive explicit-pulsed negative setup time latches. Simulations using 45nm IBM/PTM device and interconnect models, clocking 1024 flip-flops show the reductions, compared to non-resonant clocking, operating from 2GHz/1.3V to 200MHz/0.5V. The PR frequency is set >3x the clock rate, needing only 1/10th the inductance of previously integrated LC resonance. Skew reductions are achieved without needing to increase the interconnect widths owing to negative set-up times.