Energy consumption in embedded systems isstrongly dominated by instruction memory organizations. Basedon this, any architectural enhancement introduced in this compo-nent will produce a significant reduction of the total energy bud-get of the system. Loop buffering is an effective scheme to reducethe energy consumption of the instruction memory organization.In this paper, a novel classification of architectural enhancementsbased on the use of loop buffer concept is presented. Using thisclassification, an energy design space exploration is performedto show the impact in the energy consumption on differentapplication scenarios. From gate-level simulations, the energyanalysis demonstrates that the instruction level paralellism ofthe system brings not only improvements in performance, butalso improvements in the energy consumption of the system.The increase in instruction level paralellism makes easy theadaptation of the sizes of the loop buffers to the sizes of theloops that form the application, because gives more freedom tocombine the execution of the loops that form the application.