This paper proposes an 11-bit two-stage hybrid-DAC for high-color-depth LCD column drivers. To save the die area, the proposed DAC is composed of a 7-bit RDAC and a 4-bit cyclic-DAC to render an 11-bit resolution. The worst DNL/INL from post-layout simulation is 0.28/0.34 LSB with 1 LSB = 2.2 mV. A three-stage class-B operational amplifier is connected as a unity-gain buffer to drive highly capacitive column lines of LCD panel. The buffer's settling time to settle within 0.2% of the final voltage is less than 4 us. This hybrid-DAC prototype is implemented using 0.35-um CMOS technology with a chip size of 1.36 mm2.