A low-power FMCW 80 GHz radar transmitter front-end chip is presented, which was fabricated in a SiGe bipolar production technology ( , ). Additionally to the fundamental 80 GHz VCO <citerefgrp><citeref refid="ref1"/></citerefgrp>, a 4:1-frequency divider (up to 100 GHz), a 23 GHz local oscillator (VCO) with a low phase noise of (1 MHz offset), a PLL-mixer and a static frequency divider is integrated together with several output buffers. This chip was designed for low power consumption (in total , i.e., 100 mA at 5 V supply voltage), which is dominated by the 80 GHz VCO due to the demands for high output power () and low phase noise (minimum at 1 MHz offset) within the total wide tuning range from 68 GHz to 92.5 GHz (). Measurements of the double-PLL system at 80 GHz showed a low phase noise of at 10 kHz offset frequency.