Nowadays, Tunnel FETs (TFETs) are being intensively investigated for their potential in achieving sub-thermal switching slopes and extremely low leakage currents. This is possible due to their reverse biased gated p-i-n diode configuration (Figs. 1a, 1b), which allows at the same time a negligible reverse saturation current when OFF and a conduction mechanism based on band-to-band tunneling of carriers when ON. In order to overcome the intrinsic limitations of TFETs, several architectures have been explored, aiming to enhance conduction by aligning the tunneling direction to the gate electric field. Among them, a promising concept has been recently proposed, called the Electron-Hole Bilayer TFET (EHBTFET), exploiting carrier tunneling through a bias-induced electron-hole bilayer. In this work, we show that through appropriate optimization of the Ge EHBTFET it is possible to achieve superior static characteristics for low supply voltage applications, when compared to a double-gate Ge MOSFET with similar geometry. The EHBTFET outperforms the MOSFET if we compare their transfer characteristics, providing an average sub-threshold slope (from 0 to |Vdd| = 0.25 V) of 30 mV/dec against 60 mV/dec and Ion/Ioff ratio of ~10^8 against ~10^4, at same |Ion| ~ 0.18 µA/µm. Considering Id-Vd plots, the EHBTFET has been optimized to linearize the quasi-exponential current increase generally observed in TFETs at low |Vd|, with remarkable results. At the same time, it shows very high output resistances at high |Vd|, whereas the MOSFET is highly affected by channel length modulation, due to short channel effects. Taking advantage of the high symmetry of p- and n- type transistor characteristics, complementary EHBTFET and MOSFET inverters have been simulated using the same width for pull-up and pull-down transistors Wn = Wp = 1 µm. Voltage transfer characteristics (VTC) of the two inverters show that the EHBTFET exhibits higher robustness with Vdd scaling down to 0.25 V, where the MOSFET has the opposite trend. Moreover, larger noise margins (NML = 131 mV, NMH = 110 mV)and doubled inverter gain (|g| = 90.13) suggest a great potential for low-voltage EHBTFET SRAM cells. The dynamic behavior of the devices is investigated by simulating the transient response of a three-stage inverter chain and ring oscillator. This study is of major importance, considering the well-known increase of the total device capacitance that TFETs have, compared to MOSFETs. As expected, time plots confirm that this increase in capacitance doubles the input-to-output voltage delay of EHBTFET inverters with respect to MOSFET , resulting in cumulative propagation delays for larger number of stages. In addition, the EHBTFET switching current has larger decay time, but is more than 4 decades lower than in MOSFET after complete switching: this allows targeting the EHBTFET as a more suitable power-saving device than MOSFET at low supply voltage and low operating frequency. In deeper analysis, ring oscillator simulations allowed the extraction of the inverter maximum frequency of operation (f): at Vdd = 0.25 V the EHBTFET is still slower than MOSFET, with 14 MHz vs. 41 MHz. The larger delay (T = 1/f) at low Vdd increases the energy delay product (EDP) of the devices, and is higher for the EHBTFET due to the increased capacitance. However, the EHBTFET is more robust for Vdd scaling. Finally, with a logic activity factor α = 0.01, we compared the energy efficiency of the two devices for several supply voltages: at low Vdd, the EHBTFET is more promising in terms of energy-saving than the MOSFET, as it keeps the leakage component far from approaching the dynamic part of the total switching energy.