This paper presents design methodology and characterization of a 60 GHz class-A power amplifier and reviews in detail its design procedure, which requires only DC and small-signal models of the active devices. Different basic amplifier topologies are compared in order to select the best suited for a given technology. The design method is applied to a 60 GHz cascode power amplifier in a 0.25 μm SiGe BiCMOS technology working with a 3.0 V supply. Measurements show a power added efficiency of 22 % and an output power of 14.7 dBm. The compact single-stage amplifier has been implemented on an overall chip area of 0.34 mm2.