The ongoing miniaturization of silicon (Si) based metal-oxide-semiconductor (MOS) devices encourages the exploration of high dielectric constant (k) materials to substitute SiO2 gate oxide. The utilization of high-k materials may assist in the reduction of excessive gate leakage current due to the direct tunneling effect [1–3]. Recently, various types of high-k materials, such as HfO2 [4], Al2O3 [5], ZrO2 [6], CeO2 [7], Y2O3 [3, 8–11], and Er2O3 [12] have been extensively explored as the gate oxide to substitute SiO2. Among these gate oxides, Y2O3 turns out to be a potential candidate to replace SiO2 due to its fascinating properties, such as high-k value (k = 15–18), large band gap (∼ 5.5 eV), large conduction band offset (∼ 2.3 eV), low lattice mismatch and good thermal stability with Si [3, 8–11]. Up to date, extensive studies on the physical properties of Y2O3 film have been carried out, but studies involving its electrical characteristics are still lacking. Thus, in this work, the effects of annealing time (15, 30 [11], 45 minutes) on the MOS characteristics of RF magnetron sputtered Y2O3 gate oxide on Si substrate have been studied. A negative flatband voltage shift was observed in a forward bias direction of the capacitance-voltage (C-V) curves (Figure 1), indicating the presence of positive charges in all of the samples. From the calculation of effective oxide charge (Qeff), a reduction in Qeff with the increment of annealing time is obtained, which is similar to the estimation of trap density from the displacement of ΔVFB (Figure 2). Besides, sample annealed for 30 minutes has a lower slow trap density (STD) than sample annealed at 15 minutes as shown in Figure 2. When the annealing time was increased, enhancement in CET value was observed (Figure 3). The increment in CET might be related to the formation of thicker interfacial layer (IL) in the sample. The reduction in Qeff, interface trap density (Dit) (Figure 4), and total interface trap density (Dtotal) (Figure 5) with the increasing of annealing time may indicate the improvement of IL quality. The highest dielectric breakdown voltage (VB) and the lowest leakage current density were obtained by sample annealed at 45 minutes (Figure 6). This might be attributed to the acquisition of the lowest Qeff, Dit, and Dtotal. All of the investigated samples were subject to Fowler-Nordheim (FN) tunneling mechanism and the barrier height (ΦB) of the respective sample was calculated from the slope of a linear region in the FN plot [In(J/E2) vs 1/E] (Figure 7). Figure 8 shows the ΦB value estimated from FN tunneling model for the investigated samples. It was perceived that the acquisition of the highest ΦB value for sample annealed for 45 minutes has resulted in the difficulty of the carrier to overcome the barrier and thus, highest VB was attained for this sample.