The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
This paper presents a novel source-body biasing technique for RF to DC voltage multipliers designed in 0.18 μm CMOS Technology for applications where CMOS integration is required. The proposed technique increases voltage gain and efficiency by cancelling body effect and reverse leakage currents. Simulation results using HSPICE software are presented to verify and illustrate the technique by applying it to different topologies tested at different frequencies. Results show that Peak Conversion Efficiencies (PCE) as high as 16.7% can be achieved.