This paper presents a charge pump phase-locked loop with an integrated power supply regulation. Two independent regulators are employed in order to provide low-sensitivity supply voltages with inherent noise suppression for analog blocks, and to afford multiple reference voltages for test and calibration process. The built-in pre-screening test and calibration system based on the deviation of a control voltage during locking state facilitates on-chip accessibility and observability. Demonstrations of a 200-MHz charge pump phase-locked loop in 0.18-μm CMOS standard technology demonstrate low-jitter and low supply sensitivity performances with test and calibration functionality.