Today the research on designing for testability is becoming very important in the filed of SoC. However, the traditional research is limited in top level of SoC. It does not really guarantee to improve the utilization of test resource of SoC and reduce the test time effectively in theory. This paper proposes that the focus of study will be extended to the IP core level. We can reduce the percentage of idle test time and achieve the minimum of test time in various IP cores through the establishment of scheduling strategy of balancing WSC (Wrapper Scan Chain) and the exchange ISC (Inter Scan Chain) heuristic algorithm. In this paper, we verify the scheduling strategy of balancing WSC in algorithm and reusability upon the ITC'02 benchmarks. The results show that the vast majority of percentage of idle test time is much less than 1% in the relationship set between the number m of balanced WSC and the test time TIP within each IP core. The results also can verify the importance of the research programme which is implemented in IP core level for improving the utilization of test resource and reducing the test time effectively in SOC.