Interface traps generated during device operation or stress is directly related to transistor electrical characteristics and reliability as well as critical to device performance. In this paper, an interface-trap model is included in the unified compact model (Xsim) in order to physically and accurately characterize the interface-trap behavior in silicon-nanowire (SiNW) MOSFETs. The interface-trap model is verified by TCAD simulation data. Very good agreement is achieved and the effect of interface traps is accurately captured in the drain-source characteristics of SiNW MOSFETs. The physical interface-trap model is readily applicable for circuit and reliability modeling with SiNW transistors as building blocks.