In this work a highly integrated, ultra-low-power BPSK receiver for short-range wireless communications is presented. The receiver consists of a power divider, two injection-locked RC oscillators with limiting buffers and an XOR output stage. The demodulation principle is based on the dynamic phase response of the two BPSK signal injected oscillators. As proof of concept, a 300 MHz receiver was implemented in a 90nm CMOS technology. The whole receiver has an active die area of 0.04 mm2, a sensitivity of -34 dBm at 1Mbps and consumes only 120 μW from 1V supply, which relates to an energy per bit of only 0.12 nJ/bit, a value which is among the best reported up-to-date for low-transmission rate systems.