This paper describes the design of a high-performance asynchronous differential equation solver, a common DSP application. The high performance is achieved by two means. First, efficient self-timed datapath elements were designed, including a self-timed carry-bypass adder with low-overhead domino completion-detection and a staggered-evaluation precharged multiplier using carry-save-addition. Second, asynchronous control circuit overhead was minimized to 12% by using an efficient 3D control circuit design style and timing assumptions to effectively hide control circuit delay. The design has been simulated in a 1.2??m two-metal HP SCMOS process and compared to comparable synchronous designs. Its average-case performance (simulated at 25??C and 5V) is estimated to be 37% faster than the synchronous worst-case performance (simulated at 100??C and 4.5V).