A 4-/16-/64-/256-QAM demodulator LSI with an all-digital carrier-recovery loop including a novel phase detector and a fractionally-/ symbol-spaced equalizer is described. The phase detector, deciding the transmitted symbol from received signal power, detects the phase error up to ??45?? and enables the loop to internally eliminate the ??80 KHz carrier-frequency offset. The fractionally-spaced equalizer is implemented at the same clock rate as the symbol-spaced equalizer by only increasing the selectors and flip-flops, though the former theoretically requires a two times faster operation than the latter. An LSI operating at a symbol rate up to 8 MBaud is successfully implemented.