Based on Weibull distribution, a statistical RLC model considering process variations for the efficient analysis interconnect delay is proposed. The statistical RLC model can be used for optimizations, like placement, interconnect synthesis and static timing analysis (STA). Although some delay models of interconnect have been presented, like Elmore, equivalent Elmore, D2M and WED, some of them have not considered the effects of inductances and every one of them have not considered the process variations. The model proposed in this paper has considered all of them. The effectiveness of the proposed model is proved through experimental results. Compared with HSPICE, the result show that the error of 50% delay is less than 1%, the error of mean and the error of the average deviation in Monte Carlo analysis are less than 1%.