The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
The demand for high-performance on-board processing in space applications drastically increased because of the discrepancy between extreme high data volume and low downlink channel capacity. Furthermore in-flight reconfigurability and dynamic partial reconfiguration enhances space applications with re-programmable hardware and at run-time adaptive functionality. Therefore it is a maintenance and performance improvement. Furthermore it enables mission specific adaptability on demand on board of S/C. Additionally dynamic partial reconfiguration is an improvement in terms of resource utilization and costs. Current space qualified reprogrammable FPGA technologies provide large logic density and have already successfully demonstrated their suitability for space applications. To achieve such an advanced dynamic partial reconfigurable system an appropriate FPGA architecture has to be chosen and the requirements to meet a high reliable system have to be analyzed. In this paper the current available reprogrammable FPGA technologies will be compared and their suitability for a dynamic partial reconfiguration will be outlined. The requirements to achieve a high reliable fault tolerant system will be presented and a framework is proposed.