The device degradation problem due to compressive STI in devices with narrow width or small diffusion length can be greatly relieved in SiGe channel devices with the post-STI epitaxy process. The (110)SiGe PMOS realizes 77% current gain over (100)Si PMOS at 1um gate width, and current gain is increased to 112% at 0.12um gate width. A 42% current improvement in (100)SiGe NMOS at 0.12um gate width is also reported. Moreover, for diffusion length ranging from 2.71um to 0.26um, less than 4% current variation is obtained in SiGe channel devices compared to the 8~12% current variation in Si channel devices. The improved layout dependence is resulted from the lower STI stress in post-STI SiGe epitaxy process.