A delay-locked loop (DLL) Integrated with an analog self-calibration circuit is presented. The proposed DLL can generate precise multiphase clocks over process corners, voltage/temperature variations and device mismatches when incorporating with the calibration circuit and variable-delay output buffers. The experimental circuit in a standard 0.35-mum CMOS process demonstrates delay mismatch between phases can be reduced from tens of pico-second to less than ten pico-seconds at 100 MHz. The prototype circuit occupies an area of 2.1 mm2, and consumes around 10.1 mW at 3.3 V.