In this work we take a control theoretic approach to the dynamic voltage/frequency scaling (DVS) in a MPSoC architecture with mixed pipelined/parallel processing. The aim is that of minimizing energy consumption with throughput guarantees. Theoretical analysis and experiments, carried out on a cycle-accurate, energy-aware, multiprocessor simulation platform, are provided. We give a dynamic model of the system behavior on the basis of which we synthesize a non-linear feedback controller for the run-time adjustment the frequencies of the processing stages. We compare, from an energy consumption viewpoint, the proposed feedback approaches with local DVS policies.