This paper describes a successful switched-capacitor implementation in CMOS process of a time-interleaved high-pass DeltaSigma modulator that is completely immune to channel offset. As a result, a simple LMS algorithm can be used to equalize the channel gain mismatch. In this parallel architecture, second-order HP DeltaSigma modulators achieving a 59dB dynamic range with a 32 times oversampling ratio at 10 MHz sampling frequency, were used. These modulators were implemented in a 0.35mum 3.3V CMOS process. The parallel system gives almost the same performance with the oversampling ratio reduced by half