Proceedings of the Design Automation & Test in Europe Conference > 1 > 1
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Abstract
Identifiers
book ISBN : | 3-9810801-1-4 |
DOI | 10.1109/DATE.2006.243941 |
Keywords
wireless sensor networks automotive electronics circuit optimisation design for manufacture electronic design automation fault simulation field programmable gate arrays formal verification hardware-software codesign integrated circuit reliability integrated circuit testing integrated memory circuits logic design low-power electronics network-on-chip reconfigurable architectures memory testing multiprocessor system-on-chip power grid analysis interconnect network analysis online testing fault tolerance model based design transaction level modeling application specific network-on-chip design analogue design automation soft error analysis concurrent testing processor design memory design reconfigurable computing design for manufacturability design for yield mixed-signal design processor self-test fault diagnosis hardware/software architectures timing analysis noise analysis automotive systems NoC architectures low power embedded architectures low power design embedded software nanotechnology circuits reliability dynamic power aware logic design defect modeling data layout optimizations resource constrained scheduling sequential optimisation Boolean matching semi-formal validation methods test data compression FPGA testing architectural level synthesis system level verification arithmetic circuit optimisation logic circuit optimisation
wireless sensor networks automotive electronics circuit optimisation design for manufacture electronic design automation fault simulation field programmable gate arrays formal verification hardware-software codesign integrated circuit reliability integrated circuit testing integrated memory circuits logic design low-power electronics network-on-chip reconfigurable architectures memory testing multiprocessor system-on-chip power grid analysis interconnect network analysis online testing fault tolerance model based design transaction level modeling application specific network-on-chip design analogue design automation soft error analysis concurrent testing processor design memory design reconfigurable computing design for manufacturability design for yield mixed-signal design processor self-test fault diagnosis hardware/software architectures timing analysis noise analysis automotive systems NoC architectures low power embedded architectures low power design embedded software nanotechnology circuits reliability dynamic power aware logic design defect modeling data layout optimizations resource constrained scheduling sequential optimisation Boolean matching semi-formal validation methods test data compression FPGA testing architectural level synthesis system level verification arithmetic circuit optimisation logic circuit optimisation