With the improvement in integrated circuits features and increase in clock frequency, it becomes necessary to make a transition to an interconnect materials with better electrical performance. The implementation of low-k materials into the 90 nm and further technology nodes has been thwarted by the lack of viable packaging solutions. To-date no solution to enable true-low-k packaging exists. Low-k materials are mechanically, chemically, thermally, and electrically less stable than the historical material of choice, SiO2. Therefore, the challenge lies not only in identifying and characterizing the candidate materials, but also in devising the best method to integrate those materials. With the trends towards finer pitches, the chip and substrate standoff reduces below 25 mum give rise to higher stress on the bumps due to CTE (coefficient of thermal expansion) mismatch. However, the use of Cu/low-k materials in BEOL (back-end-of-line) of the IC has more adverse impact of having chip side failure and it is critical to have a good UBM integrity and compliant structure to handle the stresses. Authors already reported the reliable flip chip packaging technology for Cu/low-k wafers with Pb-free solder (Mercado, 2003). In this paper, new dicing concept of PEDL (polymer encapsulated dicing line) was introduced to improve the dicing yield of Cu/low-k wafers. According to the mechanical simulation, PEDL showed the less die corner stress than normal dies. Generally the stress was concentrated on the corner of chip in case of flip chip packaging. And the stress brings out the internal crack propagation or underfill delamination. Test vehicles are fabricated with 4 layer Cu/low-k devices and 150mum pitch flip chip bump. MSL (moisture sensitivity level) test is carried out after assembly of flip chip packaging with 35mmtimes35mm flip chip BGA substrate. The details of reliability results of flip chip packaging are presented in the manuscript