This paper describes a new differential current memory cell which is based on the Miller effect and an interleaved ADC architecture. As far as the CMC is concerned, it was pointed out that the opamp design is not an issue to achieve high performances. Simulation results show good performances for sampling rates up to 20MS/s (assuming 22ns for both sampling and holding mode) and relatively large current input signals of mnplus200muA. The originality of the proposed interleaved ADC architecture consists in improving the ADC sampling rate with minimum penalty to SNR performances