Use of the linearising current-mode cell (LCMC) concept is presented to design highly linear differential pair transconductors compatible with standard CMOS technology. The linearity an input voltage range of the proposed circuits are significantly improved over those of the conventional source-coupled differential pair biased by a current sink. The SPICE simulation results show that, for a power supply of +or-5 V, the linearity error is less than 0.2 Omega over +or-4 V differential input range.<<ETX>>