It is shown by TCAD simulations how the gate-induced drain leakage which dominates the OFF-current in 22nm double-gate and 32nm single-gate SOI nFETs with high-K gate stacks, can be minimized by proper variations of the junction profiles. Based on a microscopic, non-local model of band-to-band tunneling, transfer characteristics are computed after systematic changes in source/drain doping, body thickness, and HfO 2 layer thickness. This is done under the constraint of a minimal degradation of the ON-current. Variations which lead to the best compromise are highlighted. The obtained results suggest the alignment of the lateral doping profile with the gate corners to be the decisive factor. It is found that the ITRS target for 22nm DG LSTP devices (10pA/μm) can be met with acceptable degradation of the ON-current.