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The scaling properties of the tunneling field effect transistor (TFET) are shown using standard 130nm, 90nm, and 65nm CMOS process flows. For the different technology nodes the temperature dependence is presented. The device characteristic does not show degradation after a combined voltage and temperature cycle. It is shown that the TFET dependence on the design parameters, i.e. channel width and...
This work presents a study on the influence of the design parameters on the ambipolar current (I AMB ) of the Tunnel Field Effect Transistors (TFETs). Using numerical device simulations, I AMB is reduced progressively by underlapping the gate and the drain, by using low-k spacers and by placing the contacts in the top and bottom configuration. It is explained that a structure with...
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