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A gate structure design for negative capacitance field effect transistors (NCFETs) is proposed. The hysteresis loop in current–voltage performances is eliminated by the nonlinear C–V dependence of polysilicon in the gate dielectrics. Design considerations and optimizations to achieve the low SS and hysteresis-free transfer were elaborated. The effects of gate-to-source/drain overlap, channel length...
In this work, a kind of negative capacitance double-gate junctionless transistor (NC-DG-JLT) with ferroelectric (FE) gate dielectric and metal-ferroelectric-metal-insulator-semiconductor (MFMIS) structure is proposed. It is demonstrated that NC-DG-JLTs can lower off-state current, improve on-state drain current, and lower subthreshold swing at the same time compared with its conventional DG JLT counterpart...
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