The parasitic bipolar transistor inherent to grounded gate nMOS transistors is modelled, accounting for the specific conditions applied by CDM ESD stress. The avalanching of both, drain and source, the triggering of snapback and the CDM-specific bipolar saturation mode are addressed. Furthermore, a fast analytical method to determine CDM ESD lumped tester parasitics from measured pulse characteristics is presented. The triggering of the grounded gate nMOS transistor under CDM is studied in detail for different gate lengths. The optimal gate length for CDM protection in advanced submicron technologies is discussed.